This invention relates to magnetic bubble (domain) memories and in particularly to a new and improved on-chip decoder for the transfer of information to and from memory.
Bubble memories having propagate elements on which bubbles propagate element-to-element in response to a rotating in-plane magnetic field are, of course, old in the art. In bubble memory arrays, these propagate elements are conventionally arranged in loops so that bubbles transferred into the loop will circulate indefinitely in said loops until transferred out. Thus, bubbles circulating in these storage loops represent information stored in memory and, when information stored in memory is transferred out of the storage loops, the presence or absence of a bubble on a propagate element is detected in a bubble detector which sends a representative signal to a utilization device.
Read and write on-chip decoding for transferring information into memory is old in the art as disclosed in the U.S. Pat. No. 3,689,902 and 3,701,125 both of which issued to Chang et al. The patented write decoder has its input connected either to a plurality of bubble domain generators, or to a single generator connected selectively to various propagation channels in the write decoder. As stated in the patents, the basic element of the decoder is an OR switch, sometimes called a port or gate, which consists of a current loop superimposed on a propagate element. The proper arrangement of these OR switches permits the selection of 2.sup.N storage loops by 2.sup.N control conductor (N pairs). The decoders have 2.sup.N double propagation paths or tracks each of which has two paths. One path connects a bubble domain generator to the storage loop while the other path terminates in an annihilator. Thus, depending upon the presence or absence of control signals, bubble domain inputs from the generators are propagated to selected storage loops or are destroyed.
FIG. 1 shows such a prior art on-chip decoder arranged to write information into memory. In FIG. 1, four tracks 10-16 of propagate elements connect four output tracks to storage loops 1-4 with four sources of bubble generators G, which generate bubbles which are then propagated on tracks past a plurality (eight shown) of transfer gates. As shown, four conductor A, A, B and B, each have two gates for decoding the information to be entered into memory. Bubbles, being propagated on the tracks, cross over control conductors and gates, and the control conductors are selectively supplied with a current pulse which switches an undesired bubble to a second track 1a-4a, which directs the bubble to an annihilator. On the other hand, a bubble in the track in a gate whose conductor is not pulsed allows the bubble to continue on to one of the decoder output tracks 1-4.
Of course, control circuitry is required for accounting for the bubbles passing through the decoder so that the proper conductors are pulsed, or not pulsed, for the particular input to the storage memory selected.
The problem with the prior art decoder is the number of conductors required to operate the gates and the associated number of off chip electronic circuits.
It is therefore an object of this invention to provide a decoder in a bubble memory in which the number of conductors and external circuits for operating the decode gates is reduced.
As will be apparent from the following description of the drawings and the preferred embodiments of the invention, reduction in the number of conductors results in a cost reduction and simplicity in operation. The cost reduction results from the fact that less space is used on the chips for metallization of the conductor runs and less bonding pads are required. A further cost reduction results because the external circuitry, which drives fewer conductor lines, can serve multiple functions thus eliminating some electronic components from the memory system.